Eliyan raises $60M for chiplet interconnects that speed up AI chips

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Eliyan has raised $60 million in funding for its chiplet interconnect technology that speeds up the processing for AI chips.

Samsung Catalyst Fund and Tiger Global Management both led the round to help the team address the challenges of development of generative AI chips. Driven by demand for AI chips, industry forecasters are calling for robust growth in the high-bandwidth memory (HBM) sector, as much as 331% increase this year, followed by 124% in 2025, according to market researcher Arete Research.

Eliyan’s UCIe-, BoW-, or UMI-compliant PHY (dubbed NuLink PHY) addresses memory and IO wall constraints on either advanced or standard packaging material. A PHY is a physical layer of the OSI model. An instantiation of PHY connects a link layer device (often called a MAC) to a physical medium such as an optical fiber or copper cable. Now it’s being applied to multi-chip solutions, which allow chip makers to connect multiple chiplets on the same device.

Eliyan’s chiplet interconnect technology achieves up to four times the performance and half the power of other solutions, the company said.

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NuLink PHY is proven on advanced process nodes, addresses both Die-to-Die and Die-to-Memory interconnect with its highly efficient performance metrics.

Existing investors also participated in the round, including Intel Capital, as well as SK Hynix, Cleveland Avenue and Mesh Ventures, among others.

The additional investment follows the company’s $40 million Series A round in 2022. It will enable Eliyan to continue its focus on the most pressing challenges facing the design and manufacturing of advanced AI chips that use multi-die architectures in either advanced packaging or standard organic substrates. Its chiplet interconnect technology allows chip makers to achieve new levels of performance and power efficiency.

In addition to die-to-die interconnect in chiplet-based designs, the company addresses the growing challenge of memory capacity and bandwidth in AI chips with its innovative Universal Memory Interface (UMI). The bi-directional interconnect method aims at the “memory wall” issue facing large, multi-die designs.

Eliyan’s cofounders.

“We are thrilled to co-lead Eliyan’s Series B round and partner with an exceptional team known for their unique expertise in interconnect and mixed signal technologies,” said Marco Chisari, head of Samsung Semiconductor Innovation Center, in a statement. “Intensive workloads and cutting-edge applications, including Generative AI and automotive, are driving the demand for more sophisticated semiconductor design and the adoption of chiplet architecture.”

UMI enables a very bandwidth-efficient connection to memory, in both standard organic substrates and advanced packaging. Given its highly efficient PHY beachfront area, UMI provides a significant increase in aggregate memory bandwidth per AI chip and major die area reduction needed for memory interfaces. Read more on UMI here.

“At a time when the explosion of AI is driving increasing connectivity needs and the semiconductor industry is undergoing a seismic shift with the rise of multi-die implementation, Eliyan is poised to revolutionize chiplet connectivity technology by unleashing the ultimate performance of chiplet-based systems,” said Srini Ananth, managing director at Intel Capital, in a statement. “Eliyan’s continued advancements in die-to-die interconnect architecture and its scalability in the AI era, truly marks a significant milestone in the larger chiplet revolution.”

Eliyan’s NuLink PHY recently taped out on TSMC’s 3nm process, targeting industry-leading performance of up to 64Gbs per link, at an unprecedented performance/power ratio.

“This investment reflects the confidence in our approach to integrating multi-chip architectures that address the critical challenges of high costs, low yield, power consumption, manufacturing complexity, and size limitations,” said Ramin Farjadrad, CEO of Eliyan, in a statement. “Our NuLink technology has achieved commercial readiness with tape outs in the most advanced processes, and is optimized for delivering the necessary high bandwidth, low latency, and low power capabilities. We thank all of our investors for their support of our vision of enabling the ultimate chiplet systems for the new AI era.”

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